1. Field of the Invention
The present invention relates to a data bus clumping circuit in a semiconductor memory device such as a dynamic RAM (Random Access Memory) capable of reading out data on a data bus at high speed, independently of variation in a power supply voltage, with a differential amplification type of read out circuit.
2. Description of the Prior Art
FIGS. 5A and 5B show conventional data bus clamping circuits used, for instance, in a semiconductor memory device as shown in FIG. 2, which will be explained later in detail.
The data bus clamping circuit of FIGS. 5A and 5B comprises an N channel type of MOS transistors (referred to as NMOS's hereinafter) 61, 62, 63 and 64 which are extremely small in mutual conductance. NMOS's 61 and 62 are connected in series between a data bus DB and a ground potential VSS. NMOS's 63 and 64 are connected in series between a data bus DB and the ground potential VSS. NMOS's 61 and 63 are operative to turn on and off in response to a row address latch signal RAS. When NMOS's 61 and 63 turn on, NMOS's 62 and 64 are operative to turn on.
FIG. 6 is a view showing operational wave forms at the time when data are read out by the data bus clamping circuits of FIGS. 5A and 5B. Now referring to FIG. 6, a readout operation for memory cell array 10 shown in FIG. 2 will be explained hereinafter.
(1) Standby period Ta
In FIG. 6, during a standby period Ta wherein a row address strobe signal RAS is given with a high level (referred to as "H" hereinafter), the row address latch signal RAS is in level VSS, both sense amplifier enabling signals SAP and SAN are in 1/2 VCCH (power supply voltage), a columnaddress decoder enabling signal YDE and a column decoding signal YD are in VSS, and bit lines BL and BL are in 1/2 VCCH.
When the row address latch signal RAS is in level VSS, NMOS's 61 and 63 in the data bus clamping circuits of FIGS. 5A and 5B are in a turn-off condition. On the other hand, in a data bus pull-up circuit 50, a circuit structure of which is shown in FIGS. 4A and 4B, NMOS's 51 and 52 each having a threshold voltage Vt are in a turn-on condition, and thus the data buses DB and DB are (VCCH-Vt) in the potential.
(2) Active period Tb
When transition of the row address strobe signal RAS to a low level (referred to as "L" hereinafter) occurs at time t1 in FIG. 6 (referred to as "L" hereinafter), the row address latch signal RAS becomes VCCH. When the row address latch signal RAS becomes VCCH, a row direction of the memory cell array 10 is selected by a row address decoder 20, so that data on the selected memory cells are read out on the bit lines BL and BL.
On the other hand, when the row address latch signal RAS changes in level from VSS to VCCH after transition of the row address strobe signal RAS to "L", NMOS's 61 to 64 in the data bus clamping circuits of FIGS. 5A and 5B become a turn-on condition. Consequently, electric charge on the data buses DB and DB is discharged, and thus potentials of the data buses DB and DB are determined between VCCH and VSS based on the resistive divisional ratio of turn-on resistance of NMOS's 51 and 52 in the data bus pull-up circuit 50 to turn-on resistance of NMOS's 61 to 64 in the data bus clamping circuits of FIGS. 5A and 5B.
At time t2, if the power supply voltage is changed from VCCH to VCCL (for example, 4 to 5 volt), the electric charge on the data buses DB and DB is discharged by the data bus clamping circuits of FIGS. 5A and 5B.
At time t3, after the data on the memory cells are read out on the bit lines BL and BL, the sense amplifier enabling signal SAP changes in level from 1/2 VCCH to VCCL and the sense amplifier enabling signal SAN changes in level from 1/2 VCCH to VSS. Those transitions of potential level cause a sense amplifier circuit 30 to amplify a minute potential difference .DELTA.V between the bit lines BL and BL.
At time t4, when the column address decoder enabling signal YDE changes in level from VSS to VCCL, a column address signal YADn is selected by a certain column address decoder 40 selected in VCCL, and the column decoding signal YD changes in level from VSS to VCCL. When the column decoding signal YD changes in level from VSS to VCCL, NMOS's 43 and 44 in the column address decoder 40 become a turn-on condition to transfer data on the bit lines BL and BL to the data bus DB and DB. As a result, produced is a potential difference corresponding to the bit line data between the complementary data bus DB and DB. Such a potential difference is amplified by a differential amplification type of readout circuit 70, and then be output as a readout data DOUT.
(3) Standby period Tc
At time t5, when the row address strobe signal RAS changes in level from "L" to "H" to become a standby period Tc, the row address latch signal RAS is in level VSS, so that the data bus clamping circuit of FIG. 5A or 5B turns off. Further, at that time, the column address decoder enabling signal YDE and the column decoding signal YD become VSS. Thus, the data bus DB and DB are electrically separated from the data bus clamping circuit and the bit lines BL and BL, and the data bus DB and DB become in potential (VCC-Vt) by the data bus pull-up circuit 50. Further, transition of the row address strobe signal RAS from "L" to "H" causes both the sense amplifier enabling signals SAP and SAN to be in 1/2 VCCL, and also causes both the bit lines BL and BL to be in 1/2 VCCL. Thus, a series of reading out operation is terminated.
This type of conventional data bus clumping circuit, however, has been associated with the following drawbacks.
According to the conventional data bus clumping circuit, during the active period Tb shown in FIG. 6, if the power supply potential VCC changes from high potential VCCH to low potential VCCL owing to variation in a power supply, potentials of the data buses DB and DB also slowly descend by the data bus clumping circuit. However, since the descent rate in potential is low, the column address decoder 40 is enabled at time t4 in course of the potential descent, so that data on the bit lines BL and BL are transferred to the data buses DB and DB, respectively. Consequently, the differential amplification type of readout circuit 70 cannot amplify at high speed the data thus transferred.
The differential amplification type of readout circuit 70 is provided with optimum potential set values VA and VB for a high speed amplification. Whereas, at time t in FIG. 6, when the differential amplification type of readout circuit 70 starts an amplification operation, the potentials of the data buses DB and DB have not descended up to the optimum potential set values VA and VB, respectively. Accordingly, the differential amplification type of readout circuit 70 can not amplify at high speed the data on the data buses DB and DB. Thus, the conventional data bus clumping circuit has been associated with such a problem that a readout speed of data slows.
In order to solve this problem, it may be considered that the potentials of the data buses DB and DB are clamped at high speed by the data bus clamping circuit. Whereas, when the column address decoder 40 is enabled, so that the bit lines BL and BL and the data buses DB and DB become conductive conditions, respectively, a current of the sense amplifier enabling signal SAP flows through P channel type of MOS transistor (referred to as PMOS hereinafter) 34 in the sense amplifier 30, NMOS 44 in the column address decoder 40 and NMOS's 63 and 64 in the data bus clamping circuits in FIGS. 5A and 5B to the earth potential VSS.
Increment of such a current brings drawbacks such as deterioration of the transistors as well as increment of an amount of consumption current. Thus, according to the conventional data bus clamping circuit, the mutual conductance of NMOS's 61-64 is set to be small. In other words, a large turn-on resistance is provided for decrement of such a current. Consequently, it is impossible to clamp the potentials of the data buses DB and DB at high speed by the data bus clamping circuit, and thus impossible to solve the problem with which the conventional device encounters.